As of 2019 110 nm rad-hard processes are available. Use of SRAM cells with extra transistors per cell than normal (which is 4T or 6T), which makes the cells more tolerant to SEUs at the associated fee of higher energy consumption and measurement per cell. Use of Edge-less CMOS transistors, which have an unconventional physical building, together with a unconventional bodily structure. Error correcting code memory (ECC reminiscence) makes use of redundant bits to check for and possibly right corrupted knowledge. Since radiation’s results injury the memory content even when the system just isn’t accessing the RAM, a “scrubber” circuit
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